Current Proceedings on Technology

Current Proceedings on Technology

HDL model simulation-based verification in a VHDLVisualizer visualization environment

Yazarlar: Dominik Macko, Katarína Jelemenská, Pavel Čičák

Cilt 1 , Sayı - , 2012 , Sayfalar -

Konular:-

Anahtar Kelimeler:Vhdl,Visualization,Simulation,Model,Environment

Özet: Throughout the world, many VHDL (Very-high-speed integrated circuit Hardware Description Language) simulators exist,but only a few of them support the visualization of VHDL model simulation. The simulation is most commonly displayed as awaveform. This representation of the visualization is sufficient for the verification of the model, however it is hard-to-read fornovice designers and it is difficult to identify the potential errors. In this paper, we present our progress in developing avisualization environment, which is able to display the simulation in the structural sphere of the model. During the simulationvisualization, the designer is able to switch between hierarchic levels of the structure and watch how the signal changesdirectly in the component that he/she wishes to verify.

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@article{2012, title={HDL model simulation-based verification in a VHDLVisualizer visualization environment}, volume={1}, number={0}, publisher={Current Proceedings on Technology }, author={Dominik Macko, Katarína Jelemenská, Pavel Čičák}, year={2012} }
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Dominik Macko, Katarína Jelemenská, Pavel Čičák. (2012). HDL model simulation-based verification in a VHDLVisualizer visualization environment (Vol. 1). Vol. 1. Current Proceedings on Technology .
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Dominik Macko, Katarína Jelemenská, Pavel Čičák. HDL Model Simulation-Based Verification in a VHDLVisualizer Visualization Environment. no. 0, Current Proceedings on Technology , 2012.
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