Current Proceedings on Technology

Yazarlar: Peter Pistek, Katarína Jelemenská, Milan Kolesár

Konular:-

Anahtar Kelimeler:Multiplexer,Multiplexer tree,Modified truth table

Özet: Low power consumption belongs to the main requirements of nowadays digital systems. One of the basic power saving concepts is the implementation complexity reduction that can be reached using circuit optimization. The n-to-1 multiplexer is generally implemented decomposed into smaller multiplexers (typically 2-to-1, but up to 16-to-1). We proposed a novel method of multiplexer tree design based on an efficient elimination of multiplexers/group of multiplexers from a circuit. The resulting circuit is made of multiplexers and basic logic gates like AND, NAND, OR, NOR, etc. Thanks to the residue variable usage we can simply eliminate the most numerous layer of multiplexer tree (i.e. in multiplexer tree composed of 2-to-1 multiplexers more than half of multiplexerscan be eliminated). The experimental results show that compared to the original non-optimized circuit the proposed method can reduce the number of required gates up to 68,4 %. In addition, the MLUT (modified lookup table) reduction was designed. 

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